1. Field of the Invention
The present invention relates generally to semiconductor technology and, more particularly, to a method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer, and a semiconductor device having double gate dielectric layers.
2. Description of the Related Art
A dramatic trend toward scaling down of a transistor in integrated circuit chips continuously requires a much thinner gate dielectric layer. The ultrathin gate dielectric layer may, however, confront many problems to be solved. A decrease in gate oxide integrity (GOI) property is one of such problems. This problem related to GOI property may be caused by plasma-induced damage that may often occur during several processes such as gate etch, metal etch, via etch, and gap fill CVD that follow a gate oxidation process.
In order to improve GOI property, an oxy-nitride layer has been used for the gate dielectric layer. FIG. 1 shows, in a cross-sectional view, a conventional semiconductor device having the oxy-nitride gate dielectric layer.
Referring to FIG. 1, a field region 11 having STI (shallow trench isolation) structure is formed in a silicon substrate 10 to define an active region. A well region 12 is formed in the substrate 10, and source/drain regions 15 having LDD (lightly doped drain) structure are formed in the active region of the substrate 10. The oxy-nitride gate dielectric layer 13 is formed between the source/drain regions 15 on the substrate 10, and further, a gate electrode 14 is formed thereon.
Normally the oxy-nitride gate dielectric layer 13 is formed using nitrogen monoxide (NO) gas during a typical gate oxidation process. Such conventional method produces an oxy-nitride layer within an oxide layer. However, this oxy-nitride layer may be distributed with very poor uniformity, and further, nitrogen atoms in the oxy-nitride layer may act as impurities that cause degradation in GOI property. For example, with enough voltage applied, plasma-induced charges trapped in the gate dielectric layer 13 eventually succumb to the electrical pressure and thereby electrons flow toward the p-type well region 12. Such a breakdown voltage may be much lowered when there is a poorly uniform layer or undesirable impurity in the gate dielectric layer.
FIG. 2 illustrates a breakdown phenomenon in the non-uniform oxy-nitride gate dielectric layer. Referring to FIG. 2, electrons 20 induced by plasma are trapped in the gate dielectric layer 13 underneath the gate electrode 14 and then flow into the p-type well 12 at the breakdown voltage. Unfortunately, this phenomenon due to plasma-induced charge may deteriorate characteristics of the semiconductor device and also drop yield and reliability of the device.